1. Field of the Invention
This invention relates to the field of semiconductor device fabrication techniques and structures and more particularly to the field of fabricating FET devices and conducting lines for interconnecting such devices thereby to provide VLSI circuits of increased density and reliability.
2. Prior Art
The semiconductor art has been concerned with reducing the size and power consumption of individual devices in integrated circuits in order to increase the logic power of these circuits per unit area. Many things have been done over the years to reduce the size of devices and improve tolerances with which they are fabricated. Such efforts have included, inter alia, fine line lithography, improved mask generation and alignment machines, improved tolerances on mask alignment, and self-aligned gates. These techniques have reduced the area required for the fabrication of the individual FET devices used in these integrated circuits. However, because of alignment tolerances, prior art FET devices must be designed with larger geometries than they would have to be if perfect mask alignment were attained. Consequently, there is a need for an improved fabrication technique for producing VLSI circuits including FET devices and conducting lines having reduced sensitivity to mask alignment and thereby affording increased density and reliability of such devices and circuits.